1. Field of the Invention
The present invention is related to a logic cell placement improving method for timing closure in a smooth manner in a layout design of a semiconductor integrated circuit.
2. Description of the related art
In connection with progress of very fine techniques, such a timing closure problem occurs in which timing designs are not completed after layouts have been designed. As methods of capable of solving this timing closure problem, optimizing methods for optimizing circuits at layout designing stages have been proposed (for instance, (L. N. Kannan, P. R. Suaris, and H. Fang, “A methodology and algorithms for post-placement delay optimization,” Proc. 31st Design Automation Conference, 1994), (M. Murofushi, T. Ishioka, M. Murakata, T. Mitsuhashi, “Layout Driven Re-synthesis for Low Power Consumption LSIs,” in Proc.34th Design Automation Conference, 1997)).
A problem owned by these solving methods occurs as follows: That is, although a circuit improvement operation is carried out based upon layout information, since correct timing information of such a circuit obtained after the circuit improvement has been made cannot be grasped unless the improved circuit is again layout-processed (layout retry process), there is such a risk that a timing violation may newly occur at a time when the improved circuit is again layout-processed. Therefore, the circuit improving operation and the layout process operation must be repeatedly carried out, resulting in the problem. Also, other methods capable of avoiding (otherwise, reducing) such repetition operations have been proposed (for instance, Japanese Laid-open patent Application No. Hei-10-284612). In the patent publication 1, while no timing violation occurs at the time when the circuit is corrected, the above-described repetition operation is avoided by previously and excessively improving the portion whose timing margin is small.
However, in the conventional technique, there is no relationship between the excessively improved amount when the circuit is improved and the layout retry method. As a result, if the circuit is excessively improved, then the improved circuit may merely endure the variations occurred when the layout process operation is retried. Thus, the conventional technique cannot completely eliminate the above-explained repetition operation, but also cannot guarantee that the repetition operation is converged. This reason is given as follows: That is, when a large number of circuits are improved with having a margin, a circuit change amount is increased, so that a layout of the improved circuit is largely changed when the layout process operation is retried. As a consequence, there is a close relationship between the layout retry method and the amount of the circuit which is excessively improved.